Technical Design Proposal: Split-Type Passive Phase-Change Thermal Armor for PCIe 5.0 SSD

Document No.: ENG-SSD-TH-2026-004
Version: Rev 6.0 (NPI Approved)
Confidentiality: Proprietary
Date: 2026-08-21

1. Project Overview

1.1 Background

A PCIe 5.0 SSD dissipates approximately 14 W under full load. In a fanless, passive cooling environment, the controller junction temperature (Tj) can easily exceed 80°C and trigger thermal throttling. This proposal adopts a "sandwich structure + HDT dual-pipe parallel + split extended fin array + Z-axis adaptive suspension" architecture to achieve fully passive, silent cooling while ensuring mass production yield and mechanical reliability.

1.2 Design Objectives

• Thermal Performance: At 35°C ambient (local in-chassis environment) and 14 W full load, controller junction temperature Tj ≤ 76°C (based on actual power distribution); also meet derating requirements for harsh chassis environments up to 45°C.
• Mechanical Compatibility: Compatible with single/double-sided M.2 2280 SSDs; no interference with adjacent PCIe slots or mainstream graphics cards; Z-axis height adaptive; pass system-level shock/drop validation to ensure M.2 connector solder joint reliability.
• Cost Control: Mass production unit cost ≤ 25 RMB.
• Noise Level: 0 dB.

2. Thermal Design

2.1 Thermal Resistance Network and Junction Temperature Prediction

The thermal resistance chain is based on the actual power dissipation path of the controller, with missing items such as spreading resistance, contact resistance, and fin efficiency now included.
Design Condition: Controller power 7.5 W, NAND/DRAM total power 6.5 W, total power 14 W; ambient temperature 35°C.

Controller Junction Temperature (35°C Ambient):
Tj = 35°C + 7.5 W × 3.38 K/W = 60.3°C

45°C Harsh Chassis Environment Derating Check (for high-end platforms with high GPU heat output):
Tj = 45°C + 7.5 W × 3.38 K/W = 70.4°C
Still below the 76°C design target and 80°C throttling threshold, with ample thermal margin.

Worst-Case Concentrated Power Check (14 W entirely applied to controller path, not encountered in practice):
Tj_max = 35°C + 14 W × 3.38 K/W = 82.3°C, exceeding the 80°C throttling threshold.
Note: This condition is for extreme verification only and is not an acceptance criterion. Under actual full load, controller power is approximately 7–8 W, and NAND/DRAM heat is conducted through multiple paths (base and backplate), keeping controller Tj stable at 60–65°C.

2.2 HDT Heatpipe System and Base Optimization

• Dual-Pipe Parallel Architecture: Two D4 sintered copper heatpipes in parallel, with a combined heat transport capacity of 16–20 W, ensuring no dry-out at 14 W full load. After flattening/bending, capacity may degrade by ~30%; measured parallel capacity must be ≥ 21 W (1.5× design margin).
• Heatpipe Direct Touch (HDT): Heatpipe bottoms are precision die-flattened and then directly contact the PCM, eliminating the intermediate copper baseplate thermal resistance. Minimum wall thickness after flattening ≥ 0.25 mm to prevent puncture.
• Z-Axis Stepped Profile: The aluminum extruded base bottom is CNC-machined to create a stepped structure—the controller area protrudes to match chip height, while NAND/DRAM areas are recessed accordingly. Different thickness interface materials ensure uniform contact pressure on all heat-generating components, eliminating contact failure due to height differences.
• HDT Bottom Surface Flatness Control (New in NPI): Die flattening alone cannot reliably meet the ≤ 0.05 mm inter-pipe gap tolerance. In NPI, a "precision flattening + micro fly-cutting" composite process is adopted: leave 0.1 mm allowance after flattening, then perform a minimal fly-cutting pass to achieve coplanarity. Ultrasonic thickness measurement is introduced to ensure the thinnest wall after machining is ≥ 0.25 mm, guaranteeing both flatness and integrity.

2.3 Fin Geometry and Convection Optimization

• Specifications: 6063 aluminum extrusion, dimensions 120 mm × 60 mm × 40 mm.
• Fin Spacing Optimization: The original 15-fin design had 3.64 mm spacing, causing boundary-layer overlap in natural convection. Revised to 12 fins, 0.6 mm thick, average spacing 4.8 mm, satisfying non-overlapping boundary-layer requirements and verified by CFD.
• Total Heat Exchange Area: Approximately 0.121 m² (including exposed base area). After fin efficiency correction, effective area ≈ 0.115 m².
• Natural Convection Coefficient: h = 7.5 W/m²·K (typical for in-chassis natural convection). R_conv = 1/(7.5 × 0.115) ≈ 1.16 K/W; with fin efficiency, 1.10 K/W is used.

3. Mechanical Design and Compatibility

3.1 Sandwich Structure

To address the single-point mounting weakness of M.2 interfaces, a symmetric clamping scheme is adopted:

• Top Heatsink: Carries the HDT heatpipes and fin array.
• Bottom Backplate: 0.6 mm 304 stainless steel stamped plate that grips the SSD rear edge.
  Insulation Design: A 0.1 mm PI film or anodized insulation layer is applied to the backplate contact surface; chip locations have relief cutouts filled with thermally conductive insulating pads, eliminating short-circuit risk.
• Fastening: Two M2 stepped screws pass through the top heatsink and bottom backplate, forming a closed clamping loop.

3.2 Z-Axis Adaptive Suspension System

• Floating Mechanism: M2 stepped screw shoulders limit at the motherboard standoff; spring-loaded screw ends provide 1.5 mm Z-axis adaptive travel.
• Pressure Control: Spring preload 18 N, total pressure 0.07–0.1 MPa, well below the BGA solder joint fracture threshold (0.5 MPa), while ensuring full wetting of the PCM interface.
  Stress Verification: Spring force application point is near the controller top surface; PCB bending stress simulation confirms no excessive bending moment on the M.2 connector.

3.3 Spatial Interference Avoidance

• Offset Extension: The cooling tower is offset 20 mm toward the chassis front/memory area to avoid PCIe slot centerlines.
• Keep-Out Verification: Via 3D CAD assembly model, maintain ≥ 5 mm clearance to thick graphics card backplates such as RTX 4090; ≥ 3 mm to memory modules and their heatsinks; avoid motherboard capacitors, inductors, and other components.
• Center of Gravity Offset and Torsional Moment: Total heatsink weight is approximately 150–200 g; with 20 mm offset in a vertically mounted motherboard, torsional moment on the M.2 connector is possible. System-level drop/shock testing will be conducted in EVT. If micro-crack risk is detected, an optional auxiliary support bracket (connecting heatsink side to motherboard screw holes) will be designed to distribute torque.

4. Manufacturing Process and Workflow

4.1 Heatpipe Manufacturing Process (Revised Sequence)

Heatpipes must be manufactured and sealed before mechanical forming to prevent wick oxidation, working fluid leakage, and tube collapse.
Correct Sequence:
Raw tube → Cleaning → Sintered wick → Working fluid charging → Evacuation and sealing → Bending → Die flattening / machining of bottom surface → Leak test

• Flattening preferably by die pressing, leaving 0.1 mm allowance, followed by CNC fly-cutting for coplanarity; inter-pipe gap ≤ 0.05 mm.
• Minimum wall thickness after flattening and machining ≥ 0.25 mm; leak test required.

4.2 Interface Materials and Pump-out Control

• Controller Area: 0.2–0.25 mm high-thermal-conductivity phase-change material (PCM) to minimize thickness and inhibit pump-out after liquefaction. A containment dam (dispensed adhesive or gasket frame) or reservoir groove is added to further prevent PCM migration.
• NAND/DRAM Area: 0.5–1.0 mm standard high-thermal-conductivity gap filler pad to absorb thickness tolerances.
• Tolerance Requirement: After HDT bottom machining, inter-pipe gap depth ≤ 0.05 mm.

4.3 Assembly Flow

1. Base Machining: Extruded aluminum base CNC-machined with stepped relief → embed dual D4 heatpipes → expansion bonding.
2. Fin Attachment: Heatpipes pass through aluminum fin holes → hydraulic expansion bonding → black anodizing.
3. Final Assembly: Apply PCM/thermal pads → place SSD → install stainless steel backplate (with insulation) → torque-lock stepped screws.

5. BOM Cost Estimate (10k Volume)

Cost Control Contingency: PCM dam dispensing, stepped spring screws, and HDT leak testing carry hidden costs. First 1000-unit pilot run scrap rate will be monitored. If overall cost exceeds limit, supplier bidding and process simplification plans will be activated to keep mass production cost within target.

6. Technical Specification Summary

7. Validation and Test Plan (EVT/DVT)

8. Risk and Mitigation

9. Conclusion

controller Tj ≤ 60.3°C (35°C ambient) or ≤ 70.4°C (45°C ambient), mass production cost 25.0 RMB, and complete mechanical compatibility and reliability validation plans. This proposal passes design review and is ready for NPI pilot production.

Prepared by: Thermal Engineering Department
Reviewed by: Technical Committee
Approved by: Program Director
Date: 2026-08-21